문병수(Byung-Soo Moon) ; 최효상(Hyo-Sang Choi)
High voltage direct current (HVDC) has gained prominence as a method for connecting renewable energy sources and interconnecting electric power systems between countries. Recently, the modular multilevel converter (MMC) has been developed and is undergoing construction worldwide. MMC-HVDC represents a new conversion technology that can address the issues of switching loss and harmonics. During a fault in the MMC-HVDC system, the fault current rises rapidly due to the discharging of the SM capacitor, making it difficult to interrupt with continuous AC side current feed. This phenomenon leads to the destruction of semiconductor devices. To resolve this issue, superconducting fault current limiters with fast response characteristics have been applied to the MMC. The SM capacitor discharge continues until all IGBTs are blocked. Generally, the IGBT block delay is about 3 ms. However, the response time of the Resistive SFCL (R-SFCL) is faster than 3 ms. In this study, the characteristics of R-SFCL and the arm inductor under multiple fault locations in a long cable of the MMC system are confirmed using PSCAD. The R-SFCL is modeled based on actual experimental data. As a result, as the inductor’s capacity increases, the peak current decreases, and the farther the fault location is, the faster the DC current reaches zero-point. Conversely, in the case of R-SFCL, as the resistance increases, the peak current decreases, and the closer the fault location is, the faster the DC current reaches zero-point.