| Title |
The Three-Level PLA Design Using EXANOR |
| Abstract |
This paper deals with the three-level PLA constructed by EXCLUSIVE-OR, AND, and OR. (abbreviated as EXANOR). Most PLA circuits have constraints on minimum chip area and minimal input lines. Thus, the reduction of PLA chip area is an important factor in design of logic circuits. In this paper, newly constructed architecture of PLA is proposed and then, its reduction effect is proved theoretically and some of selected examples are illustrated for designing three-level PLA circuits. |