| Title |
An Analytical Model of Maximum Simultaneous Switching Noise for Ground Interconnection Networks in CMOS Systems |
| Authors |
김정학(Kim, Jung-Hak) ; 백종흠(Baek, Jong-Humn) ; 김석윤(Kim, Seok-Yoon) |
| Keywords |
CMOS ; Switching Noise ; Ground Interconnection Networks ; Maximum Simultaneous Switching Noise |
| Abstract |
This paper presents an efficient and simple method for analyzine maximum simultaneous switching noise (SSN) on ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression, we use {α}-power law MOS model and Taylor's series approximation. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that exist some output drivers not in transition. |