| Title |
An ASIC Implementation of Synchronized Phasor Measurement Unit based on Sliding-DFT |
| Authors |
김종윤(Kim, Chong-Yun) ; 장태규(Chang, Tae-Gyu) ; 김재화(Kim, Jae-Hwa) |
| Keywords |
Sliding-DFT ; Phasor measurement ; ASIC |
| Abstract |
This paper presents an implementation method of multi-channel synchronized phasor measurement device, which is based on the ASIC implementation of the sliding-DFT. A time-shared multiplier structure is proposed to minimize the number of gates required for the implementation. The design is verified by the timing simulation of its operation. The effect of coefficient approximation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations. |