| Title |
Distributed Arithmetic Adaptive Filter Structure for Low-power Digital Hearing Aid Processor Implementation |
| Keywords |
디지털 보청기 ; 주파수 샘플링 ; 감음신경성 난청 Distributed Arithmetic |
| Abstract |
The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation. |