| Title |
Design of High Speed Encryption/Decryption Hardware for Block Cipher ARIA |
| Authors |
하성주(Ha, Seong-Ju) ; 이종호(Lee, Chong-Ho) |
| Keywords |
ARIA ; Cryptography ; FPGA ; Pipeline ; Encrypt |
| Abstract |
With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz. |