| Title |
A Test Vector Reordering for Switching Activity Reduction During Test Operation Considering Fanout |
| Authors |
이재훈(Lee, Jae-Hoon) ; 백철기(Baek, Chul-Ki) ; 김인수(Kim, In-Soo) ; 민형복(Min, Hyoung-Bok) |
| DOI |
https://doi.org/10.5370/KIEE.2011.60.5.1043 |
| Keywords |
Test vector ; Power consumption ; Fanout count ; Vector reordering ; Hamming distance |
| Abstract |
Test vector reordering is a very effective way to reduce power consumption during test application. But, it is time-consuming and complicated processes, and it does not consider internal circuit structure, which may limit the effectiveness. In this paper, we order test vectors using fanout count of primary inputs that consider the internal circuit structure, which may reduce the switching activity. Then, we reorder test test vectors again by using Hamming distance between test vectors. We proposed FOVO algorithm to perform these two ideas. FOVO is an effective way to reduce power consumption during test application. The algorithm is applied to benchmark circuits and we get an average of 3.5% or more reduction of the power consumption. |