| Title |
Memory Allocation-based VLSI Design for HEVC Deblocking Filter |
| Authors |
김현준(Hyunjun Kim) ; 배종우(Jongwoo Bae) |
| DOI |
https://doi.org/10.5370/KIEE.2020.69.11.1755 |
| Keywords |
H.265/HEVC; Deblocking Filter; Parallel Processing; VLSI; Memory Allocation |
| Abstract |
In this paper, we propose a high-performance VLSI architecture and memory allocation algorithm for HEVC Deblocking Filter. For high-performance VLSI design, a parallel architecture is employed. Our architecture employs 8 parallel filters and 4-stage pipeline to meet the high-performance video requirements. In the implementation of highly parallel VLSI architecture, high bandwidth and low latency memory access is very important. A novel memory allocation algorithm is proposed to reduce the on-chip SRAM access conflicts between the parallel filters. By storing 4x4 pixel blocks used for the computation of parallel filters into different SRAM blocks, the data for horizontal and vertical filtering can be accessed without conflicts. Therefore, the maximum on-chip SRAM throughput is maintained during the filtering computation. The proposed architecture can process video of 16K (15360x8640) at 60fps in real time. The VLSI implementation of the proposed architecture operates at 140MHz and the gate count is 244K in TSMC 65nm process. Compared with the previous works, the proposed work shows the performance improvement of 90%. |